Implementation and analysis of a 15-Level inverter topology With reduced switch count
Document Type
Article
Publication Date
1-1-2021
Abstract
Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.
Keywords
Topology, Switches, Through-silicon vias, Power harmonic filters, Multilevel inverters, Capacitors, Voltage control, Multilevel inverters, Nearest level control (NLC), Power converters, Total harmonic distortion (THD)
Divisions
sch_ecs
Funders
Qatar University-Marubeni Concept to Prototype Development Research grant from the Qatar University (MCTP-CENG-2020-2)
Publication Title
IEEE Access
Volume
9
Publisher
Institute of Electrical and Electronics Engineers
Publisher Location
445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA