Date of Award
1-1-2005
Thesis Type
undergraduates
Document Type
Thesis
Divisions
fsktm
Department
Faculty of Computer Science & Information Technology
Institution
University of Malaya
Abstract
This project is about the development of Smart Transducer Interface Module in hardware. The IEEE1451.2 smart sensor approach specifies a 'plug and play' capability in a transducer module, which is achieved through transducer electronic data sheet (TEDS). It specifies a digital interface to access TEDS and transducer are defined. This STIM will be implemented using VHSIC Hardware Description Language (VHDL). Peak FPGA software. This report will comprise the ST1M phase from the design phase of main state machine until the end of testing phase.
Note
Academic Exercise (Bachelor’s Degree) - Faculty of Computer Science & Information Technology, 2004/2005.
Recommended Citation
Marina, Haryati Mohammad, "Smart transducer interface module (main state machine VHDL) / Marina Haryati Mohammad" (2005). Student Works (2000-2009). 2653.
https://knova.um.edu.my/student_works_2000s/2653