Evaluation and perspective of analog low-dropout voltage regulators: A review
Document Type
Article
Publication Date
1-1-2022
Abstract
Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.
Keywords
Internet of Things, Capacitors, Voltage control, Batteries, Transient analysis, Power system management, Phasor measurement units, Power supplies, Integrated circuits, Linear low-dropout regulators (LDOs), power management integrated circuits (PMICs), analog LDOs (ALDO), capacitor-less output, adaptive biasing, bulk modulation, power supply rejection (PSR), flipped voltage follower (FVF), charge pump
Divisions
fac_eng
Funders
Research University (RU) [GPF056B-2020] [MG012-2022],Science and Technology Development Fund, Macau, SAR [FDCT 0036/2020/AGJ],SKL-AMSV
Publication Title
IEEE Access
Volume
10
Publisher
Institute of Electrical and Electronics Engineers
Publisher Location
445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA