A 27-dBm, 0.92-GHz CMOS power amplifier with mode switching and a High-Q Compact Inductor (HQCI) achieving a 30 back-off PAE
Document Type
Article
Publication Date
1-1-2023
Abstract
This brief reports a 0.92-GHz two-stage power amplifier (PA) in 130-nm CMOS process with improved backoff power efficiency and linearity. The two key techniques are: a switching mechanism for adaptive device sizing of the power stage, and a high-Q compact inductor (HQCI). The PA is designed to operate in low power (LP) mode and high power (HP) mode by using an NMOS pass transistor as a switch. The PA measures a peak output power (Pout) of 27 dBm with a peak power added efficiency (PAE) of 44%. The maximum linear output power reaches 21.5 dBm thanks to our unique HQCIbased output-matching network. At the back-off output power, a 10% increment in PAE is achieved by switching the size of the power stage with the MOS switch. Maximum Pout of 21.5 dBm is measured below -30 dBc ACLR and 4% EVM for the 16-QAM/20-MHz input modulated signal. The PA has an overall chip size of 1.382 x 1.425 mm(2).
Keywords
Adaptive size, Back-off efficiency, CMOS, Intermodulation, linearity, Matching networks, Power amplifier (PA), Q-factor, Switching, Spiral inductor, Sub-GHz
Divisions
sch_ecs
Funders
Ministry of Education, Malaysia (FRGS/1/2019/TK04/USM/02/14),Research University (Individual) (RUI 1001/PCEDEC/8014079)
Publication Title
IEEE Transactions on Circuits and Systems II: Express Briefs
Volume
70
Issue
1
Publisher
Institute of Electrical and Electronics Engineers
Publisher Location
445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA