Effect of integrated anneal optimizations of electroplated Cu thin films interconnects
Document Type
Article
Publication Date
11-1-2020
Abstract
The significance of this paper is to emphasize wafer scale electrochemical plating process optimizations to demonstrate yield-limiting defects reduction. A multiple process enhancement has been implemented to reduce metal ``stress-induced'' voids, crater defects, Cu mound, as well as other killer defects. The troubleshooting is involving thermal anneal conditions with the modifications of in-situ anneal to integrated helium anneal by demonstrating capability of ramp rates during heating and cooling stages. Result shows a significant defects reduction and reveals the dependence of anneal soak time particularly for types of defects. Due to this integration of concerns, we further investigate the adoption of integrated diffuser to quantify the best degree of uniformity and high resistivity to enhance an even current distribution on the wafer. The results show that uniformity of the deposited film has been improved significantly with an increasing trend with anolyte lifetime. The origin of yield-limiting ECP defects of various range soaking time effects after CMP partial polish was identified and greatly overcome with the improved ECP system comprising an integrated modification.
Keywords
Integrated circuit interconnects, Reduction, WSI circuits
Divisions
nanocat
Publication Title
Microelectronics Reliability
Volume
114
Issue
SI
Publisher
Elsevier
Publisher Location
THE BOULEVARD, LANGFORD LANE, KIDLINGTON, OXFORD OX5 1GB, ENGLAND