Linearity improvement of differential CMOS low noise amplifier
Document Type
Article
Publication Date
1-1-2019
Abstract
This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S21 gain of 18.56 dB, noise figure (NF) of 1.85 dB, S11 of −27.63 dB, S22 of-34.33 dB, S12 of −37.09 dB and IIP3 of-7.79 dBm. © 2019, Institute of Advanced Engineering and Science. All rights reserved.
Keywords
CMOS, Differential, Linearity, Low noise amplifier (LNA), Noise figure (NF)
Divisions
fac_eng
Publication Title
Indonesian Journal of Electrical Engineering and Computer Science
Volume
14
Issue
1
Publisher
Institute of Advanced Engineering and Science