A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset
Document Type
Article
Publication Date
1-1-2019
Abstract
The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary $-g_{m}$ NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of-120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm2 excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems. © 2013 IEEE.
Keywords
capacitive source degeneration (CSD), Class-C VCO, CMOS, gate bias, phase noise (PN), start-up
Divisions
fac_eng
Funders
Fundamental Research Grant (FRGS) from the University of Malaya under Grant FP049-2017A,CEDEC, Universiti Sains Malaysia, under Grant RUI 1001/PCEDEC/8014079 and Grant 304/PCEDEC/6315056,Talent Corporation Malaysia
Publication Title
IEEE Access
Volume
7
Publisher
Institute of Electrical and Electronics Engineers