Document Type
Conference Item
Publication Date
1-1-2011
Abstract
This paper presents the feasibility challenges of designing dc-dc buck and boost converter in nano-scale. With the gradual development of VLSI design platforms, new issues have been introduced and presented to the power electronics circuit experts and VLSI engineers. Today's VLSI industry has reached the technology well within the nano-meter range. The consequence of implementing the basic power electronics converter topology such as buck and boost converter into this technology is discussed in this paper. It also covers the optimization issues between conduction modes, switching frequencies, efficiency and chip area. Fabrication issues are discussed, with the limitations of use of elements such as inductor, capacitors and resistors. Tradeoffs between chip area and performance are highlighted. Design challenge for optimum switching frequency, off the chip capacitor, and strategies to minimize switching and conduction losses are also discussed.
Keywords
Boost converter, Dc-Dc Buck, Efficiency, Switching frequency, VLSI design, Buck-and-boost converter, Chip areas, Chip capacitor, Conduction loss, Conduction mode, Design challenges, Nano scale, Power electronics circuits, Power electronics converters, VLSI industry, VLSI technology Capacitors, DC power transmission, Design, Electron devices, Optimization, Power electronics, DC-DC converters.
Divisions
fac_eng
Event Title
12th International Conference and Seminar on Micro/Nanotechnologies and Electron Devices, EDM'2011
Event Location
Erlagol, Altai
Event Type
conference
Additional Information
Conference code: 86549 Export Date: 16 November 2012 Source: Scopus Art. No.: 6006912 doi: 10.1109/EDM.2011.6006912 Language of Original Document: English Correspondence Address: Iqbal, S.M.A.; University of Malaya, Kuala Lumpur, Malaysia References: Musunuri, S., Chapman, P.L., Optimization issues for fully-integrated CMOS DC-DC converters (2002) Conference Record - IAS Annual Meeting (IEEE Industry Applications Society), 4, pp. 2405-2410; Fujita, S., Nano-electronics Challenge Chip Designers Meet Real Nano-electronics in 2010s?, , Toshiba Corporation, Corporate R&D Center, Kawasaki, Japan shinobu. fujita@toshiba. co. jp/; Alimadadi, M., Sheikhaei, S., Lemieux, G., Mirabbasi, S., Palmer, P., A 3 GHZ switching DC-DC converter using clock-tree charge-recycling in 90 nm CMOS with integrated output filter (2007) IEEE ISSCC Dig. Tech. Papers, pp. 532-533; Chakraborty, A., Emadi, A., Quantum sizing of power electronics: A trend towards miniaturization of power electronic systems and equipments (2005) Material Research Society Symposium Proceedings, 872. , Materials Research Society, pages: J18, 28. 1-J18. 28 6; Shi, C., Walker, B.C., Zeisel, E., Hu, B., McAllister, G.H., A highly integrated power management IC for advanced mobile applications (2007) IEEE Journal of Solid-State Circuits, 42 (8), pp. 1723-1731. , DOI 10.1109/JSSC.2007.900284; Munsuri, S., Chapman, P.L., Multi layer spiral inductor design for monolithic dc-dc converters (2003) Proc. Conf. Record IEEE Industrial Applications Society Annu. Conf., pp. 1270-1275; Hazucha, P., Schromm, G., Hahn, J., A 233-MHz 80-87 Efficient Four Phase Dc-Dc converter utilizing Air-Core Inductors on package (2005) IEEE Journal of Solid State Circuits, 40 (4). , April; Zou, J., Chen, J., Liu, C., Schutt-Aine, J.E., Plastic deformation magnetic assembly (PDMA) of out-of-plane microstructures: Technology and application (2001) Journal of Microelectromechanical Systems, 10 (2), pp. 302-309. , DOI 10.1109/84.925791, PII S105771570104255X; Abedinpour, S., Trivedi, M., Shenai, K., DC-DC power converter for monolithic implementation (2000) Conference Record - IAS Annual Meeting (IEEE Industry Applications Society), 4, pp. 2471-2475 Sponsors: IEEE Russia Siberia Section; IEEE Novosibirsk Joint ED/MTT/CPMT/COM/SSC Chapter; IEEE Novosibirsk State Technical University Student Branch; IEEE Electron Devices