NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations
Document Type
Article
Publication Date
1-1-2010
Abstract
Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased. (C) 2010 Elsevier Ltd. All rights reserved.
Publication Title
Microelectronics Reliability
Volume
50
Issue
9-11,
Publisher
Elsevier
Publisher Location
THE BOULEVARD, LANGFORD LANE, KIDLINGTON, OXFORD OX5 1GB, ENGLAND
Additional Information
21st European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Gaeta, ITALY, OCT 11-15, 2010