Document Type
Conference Item
Publication Date
1-1-2009
Abstract
We show the realization of 40 Gbit/s on-off-keyed system that can be recovered at 5.71 GHz clock using duty cycle division multiplexing technique with the receiver sensitivity of -22.1 dBm. ©2008 Optical Society of America.
Keywords
40-Gbit/s, Clock recovery circuits, Duty cycles, Multiplexing techniques, Receiver sensitivity, Multiplexing.
Divisions
fac_eng
Volume
2009-S
Event Title
2009 Asia Communications and Photonics Conference and Exhibition, ACP 2009
Event Location
Shanghai
Event Dates
2009
Event Type
conference
Additional Information
Conference code: 79515 Export Date: 31 January 2013 Source: Scopus Art. No.: 5377113 Language of Original Document: English Correspondence Address: Amouzad Mahdiraji, G.; Department of Computer and Communication Systems Engineering, University Putra Malaysia, 43400 Serdang, Selangor, Malaysia; email: ghafouram@gmail.com References: Gnauck, A.H., et al. aI. (2008) J. Lightwave Technology, 26, pp. 79-84; Zhou, X., (2008) aI., in proc. OFC/NFOEC, , Paper PDP1; Jansen, S.L., (2008) aI., in proc. OFC/NFOEC, , Paper PDP2; Mahdiraji, G.A., (2008) proc. NCTT-MCP; Abdullah, M.K., aI., in proc, WOCN 2007, pp. 1-4; Razavi, B., in IEEE (2002) Communications Magazine, 40, pp. 94-101; Mahdiraji, G.A., et al. aI. Optical Review, , In press; Winzer, P.J., Essiambre, R.J., (2006) J. Lightwave Technology, 24, pp. 4711-4728