High-Speed shortest path co-processor design
Document Type
Conference Item
Publication Date
1-1-2009
Abstract
Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior.
Keywords
Shortest Path, A-Star Algorithm, FPGA Implementation
Recommended Citation
Idris, Mohd Yamani Idna; Abu Bakar, Suraya; Tamil, Emran Mohd; Razak, Zaidi; and Noor, Noorzaily Mohamed, "High-Speed shortest path co-processor design" (2009). Research Publications (2006 to 2010). 2008.
https://knova.um.edu.my/research_publications_2006_2010/2008
Divisions
fsktm
Event Title
3rd Asia International Conference on Modelling and Simulation
Event Location
Bali, Indonesia
Event Dates
25-29 May 2009
Event Type
conference
Additional Information
Univ Malaya, Dept Syst & Comp Technol, Fac Comp Sci & Informat Technol, Kuala Lumpur, Malaysia