A bit-serial sum of absolute difference accelerator for variable block size motion estimation of H.264
Document Type
Conference Item
Publication Date
1-1-2009
Abstract
Bit-serial architectures offer a number of attractive features over their bit-parallel counterparts such as smaller area cost, lower density interconnection, a reduced number of pins, higher clock frequency, simpler routing and etc. These attractive features make them suitable for using in VLSI design and reduce overall production cost. In this paper, we propose the first least significant bit (LSB) bit-serial sum of absolute difference (SAD) hardware accelerator for integer variable block size motion estimation (VBSME) of H.264. This hardware accelerator is based on a previous state-of-art bit-parallel architecture namely propagate partial SAD. In order to reduce area cost and improve throughput, pixel truncation technique is adopted. Due to the bit-serial pipeline architecture and using small processing elements, our architecture works at much higher clock frequency (at least 4 times) and reduces area cost about 32% compared with its bit-parallel counterpart. The proposed hardware accelerator can be used in different disciplines from low bit rate to high bit rate by making a tradeoff between the degree of parallelism or using fast algorithm or a combination of both.
Keywords
Computer Science, Engineering
Divisions
fsktm
Event Title
Conference on Innovative Technologies in Intelligent Systems and Industrial Applications
Event Location
Kuala Lumpur
Event Dates
JUL 25-26, 2009
Event Type
conference
Additional Information
Univ Malaya, Dept Comp Syst & Technol, Fac Comp Sci & Informat Technol, Kuala Lumpur 50603, Malaysia