Analysing random access memory chip yield performance

Author

• Choy Sar Kam

Date of Award

1-1-2000

Thesis Type

Masters

Document Type

Thesis

Divisions

Faculty of Business and Economics

Department

-

Institution

Universiti Malaya

Abstract

Despite advances in integrated circuits (IC) equipment and fabrication techniques, there still exist random fluctuations or statistical disturbances in any IC manufacturing facility. which can adversely affect the production yield. Actually devices and circuits are being designed with increasingly tighter parameter and performance margins. As a result, chip performance becomes even more sensitive to the statistical variations, and this may result in low production yield. One of the significant detractors of cost in a manufacturing line is yield loss due to contamination and the time required to increase the yield to profitable levels. Yield loss in a manufacturing line is determined by the various attributes of fabrication, product testing and failure analysis. This research attempts to determine whether there are any significant differences in the average yield by tester, by day and by test insert at each different level of temperature i.e. TOS, TLO and THI test insert. This paper also attempts to examine the yield across the various tests and investigated the major defect type that contributed to yield loss.

Initial

snms

Additional Information

Dissertation (M.A) -- Faculty of Business and Economics, Universiti Malaya, 2000

Recommended Citation

Kam, Choy Sar, "Analysing random access memory chip yield performance" (2000). Student Works (2000-2009). 261.
https://knova.um.edu.my/student_works_2000s/261

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.